Two-Dimensional Convolution on the SCC

Convolution is one of the most widely used digital signal processing operations. This work aims to distribute twodimensional convolution operation across Intel’s Single-Chip Cloud Computer (SCC), an experimental processor created by Intel Labs. This platform enables experiments with varying both the data sizes and the physical parameters of the platform such as voltage, frequency, and number of cores. The program can also be optimized subject to power and energy considerations. We find that implementing the convolution operation on the SCC can reduce the calculation time but results in a communication bottleneck. We find that calculations should be run at a lower frequency to reduce energy consumption, while communications should be run at a higher frequency to reduce execution time. Current applications are in the area of early vision using a Gaussian pyramid, while we aim to expand the study to additional image processing areas. Keywords—Convolution; SCC; FFT; Parallelism; DVFS